Hierarchical RTL-based combinatorial SER estimation

With increased device integration and a gradual trend toward higher operating frequencies, the effect of radiation induced transients in combinatorial logic (SETs) can no longer be ignored. Electrical, logical and temporal masking prevent the majority of SETs from becoming functional failures. Current work on SET analysis starts from a gate-level circuit representation, however, in an industrial design cycle, by the time a gate-level netlist is available, it is too late to make design changes. We propose a hierarchical SET analysis methodology that can be applied at the RTL level. The SET sensitivity of the cell library and the masking characteristics of standard combinatorial design blocks are pre-characterized and stored in compact models. The SET sensitivity of a complex circuit is then calculated by decomposing it into blocks and combining the compact SET models. Experimental results are presented for an ALU implemented in the NanGate library.