Ultra-low voltage and high speed NP domino carry propagation chain

In this paper, an Ultra Low Voltage NP domino logic style is presented to perform a 32 bit computation in a carry propagation chain. The presented logic style is targeted to operate at the supply voltages near the sub-threshold regime. Simulated results of 32-bit proposed carry chain compared to the conventional carry chain conclude that the proposed approach offers a superb improvement in terms of speed and EDP. The proposed carry chain has a relative delay and EDP of only 2.68% and 8% respectively compared to the conventional carry chain. The 32-bit ULV NP domino carry chain using 90nm TSMC CMOS process technology with a supply voltage of 300mV could be operated at a clock frequency of 50MHz.