Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) cell and read-disturb-free temperature-aware current-mode read scheme

Resistive RAM (RRAM) faces two major design challenges: 1) cell area versus write current requirements; 2) cell current (I
_CELL
) versus read disturbance. An RRAM using logic-process-based vertical parasitic-BJT (VPBJT) switches and correspondent cell array (VPBJT-CA) can achieve 4.5+x smaller macro area. To overcome temperature-dependent fluctuation in the base-emitter voltage difference (V
_BE
) of BJT, this work proposes a thermal-aware bitline (BL) voltage bias (V
_BL-R
) scheme (TABB) for current-mode read with 4.7x larger I
_CELL
, and a 1.6x faster read speed. Fabricated 0.18um 1Mb and 65nm 2Mb VPBJT RRAM macros confirm the efficacy of the temperature-aware V
_BL-R
, resulting in the fastest (sub-5ns) random read speed among reported Mb-scaled NVM macros.