A new low cost fingerprint recognition system on FPGA

This paper describes a new approach to fingerprint recognition problem, proposing a low cost system, implemented by FPGA. The work done shows the feasibility of having a miniaturized device, thanks to an ad-hoc architecture design, that can be embedded in the sensor. This kind of system has therefore the advantage to be an object with a high degree of diffusion, through the implementation by a reduced cost hardware (like entry-level FPGA). The proposed system maintains the same identification rate of classic solutions, but with best response time perceived at user, thanks to a new algorithm, based on binary operations and developed in order to lighten the computational architecture effort, at the expense of information redundancy in the database. The architecture has been organized with a high parallelism degree to handle information overhead and ensure a very fast response time. Features (specialized information) extraction is obtained by spatial binary filtering. Matching step is based on Euclidean distance between features vectors. A first prototype has been implemented on the Xilinx Virtex 4 Evaluation Board and tested with positive results. The new system shows an identification user rate greater than 97% and a performance improvement of 3 orders of magnitude, in comparison to the test environment set up as reference. The computational hardware cost can be further reduced, because the architecture is scalable towards inexpensive FPGA devices like Xilinx Spartan family, without losing improvement of response time.