Structural and compositional optimization of advanced fan-in WLCSPs base on FEA simulation

During the past ten years, fan-in wafer-level chip scale packages (WLCSPs) have extended its application into most of the portable handheld electronic devices, such as smart phones and tablets. All the applications of fan-in WLCSP were limited to devices with smaller die size and lower pin counts. Recently, some new applications with advanced silicon technology nodes impose new challenges on fan-in WLCSPs which is larger die size and high pin counts. These new requirements of fan-in WLCSPs make it hard to pass the end customer's board level reliability test. In this paper, the finite element analysis (FEA) method is adopted to explore the impacts of structure design and material selection on the board level reliability of fan-in WLCSPs with large die size and high I/O count. The WLCSP with Cu pillar post and surface encapsulation layer shows better solder ball thermal fatigue life and the recommendation of encapsulation material selection is given in this study.