Die-to-die and within-die fabrication variation of 65nm CMOS technology PMOS transistors

Study and understanding of transistor and circuit variations caused by the fabrication process has become an important factor for integrated circuits as the device dimensions become smaller. Effects on clock frequency and IC performance caused by die-to-die and within-die variations have made it important to incorporate process variations in circuit simulators to correctly model the working of the present IC technology. This paper demonstrates the microscopic parameter variation modeling of die-to-die and within-die variations for 65nm CMOS fabrication technology by using the HiSIM surface-potential-based compact model. It is found that for accurate variation modeling of V
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and I
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from die-to-die and within-die primary consideration of only four parameters, namely substrate doping (NSUBC), pocket-implantation doping (NSUBP), carrier mobility degradation due to gate-interface roughness (MUESR1) and channel length change (XLD) is sufficient. In addition to these, modeling of within-die variation requires inclusion of a small variation for a fifth parameter describing the depletion charge contribution for the effective-electric field (NDEP). Variation analysis is done for wide p-MOSFETs (W=10µm) as a function of gate length.