Research on CMOS inverter latch-up triggered by nMOS channel capacitance under HPM interference

By analyzing the current and voltage at the inverter ports and devices simulation, the latch-up effects and bit-error of CMOS under HPM interference were researched. The simulation results show that a (dis)charge current was flowing in the substrate of the inverter because of the gate-to-body nMOS channel capacitance when Vin varied in the region Vin<;0. When the charge current was large enough to have a b ig voltage drop at substrate resistance, the pn (p-substrate, nMOS source) junction turned on. And due to the high voltage at nMOS drain, the npn (nMOS source, p-substrate, nMOS drain) transistor turned on at first and output voltage Vo decreased, causing a bit error. With more HPM pulses, V
_O
decreased to a small value and the npn (nMOS source, p-substrate, n-well) transistor turned on due to the high voltage at n-well, making the latch-up happen. This was confirmed by the simulation results and experiment results.