UTBB with ground-plane dopant-segregated schottky barrier SOI MOSFET for thermally efficient low-variability nanoscale CMOS circuits

In this paper, a comparative study on self-heating effect, scalability, threshold voltage variability and CMOS logic performance of dopant-segregated Schottky barrier (DSSB) ultrathin body (UTB) thick buried oxide (BOX) and DSSB UTB thin BOX (UTBB) silicon-on-insulator (SOI) MOSFETs has been carried out by using the two dimensional MEDICI simulator. A novel DSSB UTBB-ground plane (GP) SOI MOSFET has also been proposed to improve the scalability and CMOS logic performance of DSSB SOI MOSFET. It has been found that, the presence of GP in DSSB UTBB-GP device not only improves the on-state drive current but also reduces the off-state leakage current of the device. Further, since the presence of GP cuts-off the path of the fringing field lines arising from the drain and the screening effect due to GP suppresses the random dopant fluctuations, both drain induced barrier lowering and threshold voltage variability in the proposed device are also low. In addition to this, the intrinsic gate delay and the static power dissipation in the case of DSSB UTBB-GP MOSFET are also reduced by ~80% and ~40% respectively over the DSSB thick BOX and DSSB UTBB SOI MOSFETs. Thus, significant reduction in self-heating effect, threshold voltage variability and the significant improvement in CMOS logic performance make the proposed device suitable for nanoscale CMOS logic circuits.