A linearity enhancement technique and its application to CMOS wideband low-noise amplifiers

Undesired harmonics have severe impacts on performance of electronic circuits and systems, especially for those used for radio frequency (RF) applications. In this paper, a harmonic cancellation technique based on combining two phase-shifted versions of the signal is introduced. As a proof-of-concept, a wideband (0.07 to 7.5 GHz) low-noise amplifier (LNA) with 3
^rd
-harmonic cancellation technique is designed and laid out in a 0.13-µm CMOS process. In this design, phase-shifter circuits are implemented using passive lumped components. Post-layout simulation results show that the LNA achieves a noise figure (NF) of 2.3 dB, S
21
of 17.9 dB while consuming 15.6 mW from a 1.2 V supply and significantly cancelling the 3
^rd
harmonic.