The design of reconfigurable Delta-Sigma modulator for software defined radio applications

A new architecture for increasing the resolution of Delta-Sigma Analog to Digital Converter (ADC) is presented. The proposed technique also reduced the area of the modulator significantly. Also the feed forward topology is used for reducing the total power consumption. The modulator has been simulated in 0.18μm standard CMOS technology with 1.8V power supply in Hspice circuit simulator. The modulator achieves the Dynamic Range of 95.6dB and 80dB for GSM and Bluetooth standards respectively while consumes 4.02mW and 4.04mW in each case.