IR-drop reduction in sub-VT circuits by de-synchronization

This paper proposes IR-drop reduction of sub-V
T
circuits by de-synchronization. The de-synchronization concept is briefly demonstrated and analyzed by a case study. Extensive IR-drop analysis' of various technology options of a 65nm CMOS family demonstrate how the noise margins are reduced due to switching noise on the supply rails. It is shown that a de-synchronized implementation reduces severe voltage drops on the supply rails by approximately 50 %, compared to a clocked design.