Automated Post-Silicon Debugging of Failing Speedpaths

Debugging of speed-limiting paths (speed paths) is a key challenge in development of Very-Large-Scale Integrated(VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speed paths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speed paths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites. In average, the diagnosis accuracy of 98:51% is achieved by our approach.