A 2.8–3.2-GHz Fractional- $N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO

A 2.8–3.2-GHz fractional-
$N$
digital PLL, implemented in 0.18-
$\mu \hbox{m}$
CMOS, is presented. The PLL architecture has the form of a classic delta-sigma fractional-
$N$
PLL. A PFD generates up and down pulses from the reference and divided-down digitally controlled oscillator (DCO) clock. The time-to-digital converter (TDC) converts the width of up pulses to digital words. The quantization noise introduced by a third-order delta-sigma modulator through the multi-modulus divider is canceled at the TDC output. A resistively interpolated ADC is employed to boost TDC resolution by a factor of five. A dither-less DCO with an inductively coupled fine-tuned varactor bank improves tuning step-size by a factor of 16.6, to 20 kHz. With a 52-MHz reference clock, a 3.2-GHz output clock, and a loop-bandwidth of 950 kHz, this prototype achieves 230-fs rms jitter, integrated from a 1-kHz to 40-MHz offset, while drawing 17 mW from a 1.8-V supply. The in-band phase noise floor is
$-\hbox{111.6 dBc/Hz}$
at a 500-kHz offset. The reference spur is
$-\hbox{75 dBc}$
and the worst-case fractional-
$N$
spur, by sweeping the multiplication ratio near 61, is
$-\hbox{55 dBc}$
. An FOM of
$-\hbox{240.4 dB}$
is achieved, and this design occupies a core area of 0.62
$\hbox{mm}^{2}$
.