Optimal transistor sizing and voltage scaling for minimal energy use at fixed performance

This paper presents a simple sizing method for low-power that is comparable in speed and simplicity to the Logical Effort sizing. Yet, the accuracy of the results is in the range of simulation errors. The method is two orders of magnitude faster than methods based on convex optimization, allowing to make quick design choices and architectural trade-offs. In the standard cell environment the method can reduce power by more than 30% over existing designs obtained using synthesis tools. These results are confirmed on examples implemented in 45nm process.