Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS process

A novel single-ended load SRAM cell is proposed in this study, where a loadless SRAM cell with write assistant loop and an isolated wordline-controlled transistor (WLC) is revealed. A shared bitline inverter is included to boost the read access speed at the minimal expense of area cost. The energy dissipation per write/read operation is found to be 0.479/0.091 fJ provided that the SRAM cells is supplied a 0.6 V VDD region using a typical 90 nm CMOS technology. The proposed cell is proved to attain the smallest area, PDP (power-delay product) and disturb-free during the memory access.