AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems

Providing low power consumption, high throughput and flexible solution is a challenge during designing process of a mobile software defined radio (SDR) system. The need for simple software generation using common programming tools becomes also a very significant factor. The paper presents the design and implementation of a chip multithreading general-purpose processor core (GPP), as the first step towards designing a flexible and programmer friendly SDR processor platform. Software tools developed for the hardware are described. The future work will be focused on designing tightly-coupled coprocessor extensions (TCC) for an application specific digital signal processing (DSP) purposes. AGATE processor system is described in form of a highly configurable library using Verilog language. The concept verification process was performed on the Xilinx Virtex-6 ML605 FPGA evaluation board. The maximum achieved frequency for the 8-thread processor is 190 MHz. Gate level simulation along with Value Change Dump (VCD) power estimation analysis were performed using three CMOS technologies: 130 nm, 90 nm and 65 nm. AGATE is capable of performing up to 0.72 DMIPS/MHz/thread with the maximum frequency of over 700 MHz and the power consumption of about 3 mW/core using 65 nm process.