A physics-based model of on-chip decoupling capacitor for accurate power integrity analysis

A physics-based equivalent circuit model of on-chip decoupling capacitor for chip modelling is proposed for use in accurate power integrity (PI) analysis. The proposed model can be easily applied to on-chip decoupling capacitor design based on the construction flow. The accuracy of the model has been verified with circuit simulation. By using this model and an incomplete one, a case study of chip-package co-simulation in H-spice environment is investigated, which successfully demonstrate the purpose of the proposed model.