FPGA implementation of hardware countermeasures

A FPGA implementation of a frequency sensor has been presented. Its main mission consists to determine when the frequency of test signal is into an allowed range. This implementation has the following configurable parameters: timing resolution and allowed range of frequency. This component operates in real-time with a delay of only one operation cycle. Countermeasures against clock glitch attacks is one of its possible applications. Experimental results in a Spartan-3AN700 device show a minimum allowed period of about 16 ns and a minimum resolution of about 4 ns. The implementation of the sensor has been verified in an electronic lock, used as a case of study. This system has been attacked with clock glitches, showing its behavior without and with sensor.