Design and Optimization of Ethernet Access System for Receiving Frames of Ethernet Based on FPGA

The purpose of this paper is to design and develop an implementation for the underlying data reception on Field Programmable Gate Arrays (FPGA) by top-down structured design. In this paper, we optimize the receiving data function of underlying Ethernet access device, reducing the requirement of the Inter-Packet Gap (IPG) for flow control. It is shown by the test that Ethernet access device don't need IPG for flow control any longer after our optimization.