Complex Floating Point—A Novel Data Word Representation for DSP Processors

This work introduces a new floating point representation for complex numbers (“Complex floating point”), and compares it to the floating point representation defined in the IEEE 754 standard, with a reference to the common DSP fixed point representation. The new suggested representation uses fewer bits than the IEEE 754, while keeping the same dynamic range and precision. A number of common DSP building blocks have been implemented. Results show that for the new representation, the ASIC silicon footprint of the arithmetic modules is bigger, by a factor of more than 10%. However, the area of the registers and memories, which usually occupy most of the DSP subsystem footprint, is 10% less. This directly leads to reduction of the cost of the ASIC. The quantization noise introduced by both representations was evaluated by running a number of common DSP algorithms, on various inputs. Results show that both representations induce a negligible quantization noise level, and the difference between them is very small: up to 0.2 dB on high SNR scenarios or for small sized vectors, and up to 2 dB on low SNR scenarios with large sized vectors. These results indicate that effectively there is no difference in quantization degradation between the two representations. By using the results of this work, a DSP processor architect can decide whether to use the IEEE 754 floating point representation, or the suggested complex floating point representation, which allows smaller memories at the expense of bigger logic and negligible quantization degradation.