Fabrication and characterization of high-performance graphene-on-diamond devices

Owing to the extremely high intrinsic thermal conductivity of graphene, the thermal bottleneck in graphene devices, which are usually fabricated on Si/SiO
₂
substrates, is the thermally resistive SiO
₂
layer. In order to increase the breakdown current density and device reliability one can consider replacing SiO
₂
with another dielectric, which has smaller thermal resistance at elevated temperatures. Here we report characteristics of the top-gate graphene field-effect transistors (G-FETs) fabricated on the ultra-nanocrystalline diamond (UNCD) layers grown by the chemical vapor deposition (CVD) on Si. We found that the graphene-on-diamond devices have increased breakdown current density by ~50% compared to the reference devices fabricated on Si/SiO
₂
and to the values reported in literature. Although UNCD/Si substrates are more thermally resistive at room temperature than Si wafers, they start to outperform Si at elevated temperatures close to the thermal breakdown point.