A low voltage low power CMOS analog multiplier

This paper presents a single low-voltage CMOS analog multiplier with low-power consumption. It consists of four voltage adders and a multiplier core. The proposed circuit is simulated with HSPICE and simulation results have shown that, under single 0.9V supply voltage, the circuit has smaller than 1.8% linearity error and 0.88% THD under the maximum-scale input 400mVp-p at both inputs. The quiescent power consumption is 58μW and the -3dB bandwidth is 70MHz.