Using a commercial PCI IP core in space flight avionics: lessons learned

The STEREO (Solar TErrestrial RElations Observatory) mission is being developed for NASA by The Johns Hopkins University Applied Physics Laboratory. The mission will employ two identical satellite observatories to observe solar phenomena, providing the first-ever 3-D stereoscopic images to study the nature of coronal mass ejections. The STEREO Interface Board, which is part of the integrated electronics module (IEM), contains electronics that handle the digital portion of the uplink and downlink communications. The functions of the Interface Board include decoding critical commands, Storing and encoding downlink information, and generating system interrupts. In addition, the Interface Board processes a variety of discrete interfaces. The STEREO IEM makes use of a Compact PCI backplane to provide communication between constituent boards. Rather than using a flight-qualified PCI chipset, the STEREO Interface Board uses a commercial PCI Intellectual Property (IP) core, integrated with a custom backend bus interface, implemented in an Actel field-programmable gate array (FPGA). An IP core is a synthesizable hardware description of a digital logic block that can be implemented in an application specific integrated circuit (ASIC) or an FPGA. The advantages of using a PCI IP core include lower expense, lower power, future reusability with smaller form factors, future reusability with increased integration, and greater customization. This will be one of the first commercial IP cores to be flown by The Johns Hopkins University Applied Physics Laboratory. This paper will explore the advantages and disadvantages of choosing the commercial IP core over a flight-qualified PCI chipset and will detail the lessons learned from the implementation, integration, and testing of the core.