A new low power full adder cell in CMOS inverter

In this paper we present a novel 1-bit full adder cell. The cell offer less power consumption in comparison with the conventional and current implementation of the full adder cell, especially at low voltages. All transitions are used for simulation to obtain the delay and the power consumption parameters. Simulation is improved in term of power consumption. The new full adder cell is simulated at 0.18_μm CMOS technology, using HSPICE.