Chip-dependent leakage Power-Aware Placement algorithm for FPGAs

Leakage power contribution in total power has been more than dynamic one in Deep Sub-Micron (DSM) technologies because of V
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decremsent. Furthermore, process variation has become as the main challenge in those technologies. In this paper, an optimized process variation-aware Field Programmable Gate Array (FPGA) placement algorithm has been proposed for leakage power reduction without any architecture modification costs. Estimated process variation-aware Clustered Logic Block (CLB) leakage power in each placement perturbs has been applied into the placement algorithm cost function. V
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variation map extraction using test circuits such as Ring Oscillators is the pre-placement processing level. Extracted map has been used for estimating leakage power and critical path delay in placement. Proposed placement algorithm that's named Total Power Aware Placement (TPAP) is implemented on VPR and power estimation and measurement has been computed by PowerModel and ACE tools in 45-nm technology. Simulation results for 20 MCNC benchmark circuits show that Power-Delay Product (PDP) parameter has been improved nearly 7.2% compared with default VPR placement algorithm. Simulations for each benchmark circuit are repeated 10 times for different variation maps. Results show that, PDP improvement standard deviation is 16.8%. As a result, proposed placement algorithm is adaptable with per-chip variation map, so proposed algorithm has been named chip-dependent algorithm.