A DFT Solution for Multi-Supply Multi-Voltage System-on-Chip

Design for testability (DFT) technology is an important part in system-on-chip (SoC) design and implementation. At present, design for testability can be realized by commercial electronic design automation tools. However, development of technology and need of market make the SoC must adopt the advanced low power solution, which presents challenges for DFT. Take a power gating and dynamic voltage scaling i.e. Multi-Supply Multi-Voltage (MSMV) SoC for example, the solution of SRAM BIST, boundary scan testing, PLL testing and logic scan testing in low power flow is described in this paper. The results of ATE testing show that this solution achieves the requirements of engineer practice.