Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. I
_d
variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, I
_on
= 1 mA/μm for I
_off
= 100 nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW, l
_on
increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.