Modified Potential Well Formed by $\hbox{Si/SiO}_{2}/ \hbox{TiN/TiO}_{2}/\hbox{SiO}_{2}/\hbox{TaN}$ for Flash Memory Application

This paper proposes a modified engineered-potentialwell (MW) for NAND flash memory application. The MW was formed by using a transitional SiO
₂
/SiO
_x
,Na-TiO
_x
,N
_y
tunnel barrier, a trap-rich TiO
₂
trapping layer, and an abrupt SiO
₂
block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N
₂
+ O
₂
thermal treatment, and the TiO
₂
trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (<; μs) at low-voltage operation (7-10 MV/cm), good P/E endurance (> 10
⁶
P/E cycles), large threshold voltage window (ΔV
_th
=M> V), as well as improved data retention at 125 °C.