FDSOI CMOS with dielectrically-isolated back gates and 30nm LG high-γ/metal gate

We present a novel fully-depleted SOI CMOS technology with dielectrically-isolated polysilicon back gates, achieved by a double BOX substrate combined with dual-depth shallow trench isolation. CMOS devices down to 30nm gate length are fabricated with high-κ/metal gates. A novel isolation structure with liners is shown to achieve robust isolation between devices and back gates. Effective back gate control of CMOS V
_T
is demonstrated, which enables dual-V
_T
design with power gating capability. Suppression of leakage and performance tolerances due to systematic process variations is discussed.