A Novel Signed Array Multiplier

A new architecture for the signed binary multiplier is presented in this paper. The proposed signed array multiplier has 54% area overhead as compared to Baugh Wooley multiplier but is 25% faster than the previous designs. The new design works with the operands in two's complement format. The multiplier is based on a basic 2 × 2 multiplier. The final product is adjusted for negative operands. The design is implemented in TSMC 0.18 um process technology node and TSPICE is used for design and simulation.