Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators

In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (V
_DD
) for logic circuits, the dependence of minimum operating voltage (V
_DDmin
) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm CMOS ring oscillators (RO's). The measured average V
_DDmin
of inverter RO's increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1 Mega, which indicates the difficulty of the V
_DD
scaling in the large scale subthreshold logic circuits. The dependence of V
_DDmin
on the number of stages is calculated with the subthreshold current model with random threshold voltage (V
_TH
) variations and compared with the measured results, which confirm the tendency of the measurement.