A new concept of self-aligned contact implantation for power devices

This paper discusses a new concept for the self-aligned contact implantation for Infineon power transistors. Instead of utilizing side wall spacers, which are formed by Tetraethylorthosilicate (TEOS) deposition followed by an anisotropic TEOS etch, the contact implantation is facilitated after the contact hole-etch process. By applying this concept, a number of process steps can be removed, which as a consequence greatly reduces the frontend production cost of a wafer. Additionally, defect density baseline as well as cycle time of the wafer is significantly reduced. Several design of experiments were performed in order to achieve the same electrical performance as compared to the original concept. Special consideration has been given on the analysis of the transistor parameters, such as `on resistance', `threshold voltage' and `transconductance'. The results are presented and discussed clearly showing the potential of the new concept.