Single event transient pulse width measurements in a 65-nm bulk CMOS technology at elevated temperatures

Soft errors are fast becoming a significant reliability issue for advanced technologies due to lower drive currents and higher operating frequencies. Single-event transients (SETs), a precursor for soft errors, show a strong dependence on operating temperature. In this work, heavy-ion induced SET pulse widths measured in a 65-nm bulk CMOS technology at temperatures ranging from 25° to 100°C with an autonomous SET capture circuit are presented. Experimental results for SETs induced in an inverter chain indicate an increase in average SET pulse width as a function of operating temperature. Unique SET test structures were also designed to differentiate between SETs induced in an nMOS transistor and those induced in a pMOS transistor. SET widths induced in a pMOS transistor increase more with temperature than SETs induced in an nMOS transistor.