A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm

This brief presents a frequency estimation algorithm (FEA) for an all-digital phase-locked loop (ADPLL) instead of the traditional binary frequency-searching algorithm. Based on the proposed FEA and a new fast-lock scheme, a fast-lock engine is designed to improve the lock-in time of an ADPLL design with two referenced clock cycles. An implementation of the proposed ADPLL design is realized by utilizing United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS technology with a core area of 300 × 250 μm
²
, consisting of an acceptable input reference clock ranging from 220 kHz to 8 MHz. The ADPLL design has a frequency range of 28-446 MHz with an 8.8-ps digitally controlled oscillator resolution. Moreover, the peak-to-peak jitter of the ADPLL achieves 70 ps, respectively.