Characterization of MOS varactor with large signal Network Analyser (LSNA) in CMOS 65nm bulk and SOI technologies

Here we report for the first time the non linear characterization and modeling of MOS varactor with a LSNA in bulk and SOI process. The comparison between large signal measurements and Harmonic Balance simulation using an electrical equivalent scheme based on small signal measurements validates the accuracy of the proposed model in this large signal conditions. Nevertheless, the capacitance behaviour versus biasing voltage is depending on signal power. From this, we develop a method for capacitance extraction. We highlight the difference of LSNA and small signal capacitance versus voltage revealing the deepth depletion with large signal conditions. Lastly, the parallel study between bulk and SOI process shows a difference on the capacitance induced by non linearities of the substrate capacitance with large signal analysis.