Modified Floating Gate and IPD Profile for Better Cell Performance of Sub-50 nm NAND Flash Memory

We report a new approach to utilize oxygen implantation on the top of the floating gate (FG) to improve the cell performance of a sub-50 nm NAND flash memory cell. This method was used to form a thin oxide layer only on the top of the FG but not on the sidewalls. It also rounded the corners of the FG. As a result, the leakage current between FG and control gate (CG) was reduced without sacrificing the gate coupling ratio (GCR). With this approach we improved Vt_sat_program and Vt_sat_erase without degrading VgVt_program and VgVt_erase on real Si.