CMOS-based high-density silicon microprobe for stress mapping in intracortical applications

This paper reports on a novel CMOS-based silicon microprobe for high-density intracortical stress mapping. In contrast to existing systems, square p-type field effect transistors (FET) with four source/drain contacts (piezo-FETs) are integrated on the slender, needle-like probe shaft. In total, 345 stress sensors are arranged in five columns (x/y-pitch of 51.4/26.6 µm) along the 180-µm-wide shaft. Measuring in-plane normal stress in silicon neural probes is envisioned to avoid probe fracture during insertion and to evaluate the probe deflection caused by brain motion after insertion. The combination with switchable electrodes will enable the simultaneous neural recording of brain activity. The paper presents the probe concept, the post-CMOS fabrication process, the piezo-FET characterization, and measurements demonstrating stress mapping in a brain model.