DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code

This paper presents a novel approach to transform DEVS models of computation into synthesizable VHDL code. By describing the transformation process thoroughly in terms of MoC timing characteristics, our approach is applicable to other discrete event based MoCs as well. The transformation engine uses rule checks to verify whether the model may be applicable to embedded real-time systems or if it may be only applicable to reduce simulation time by hardware execution. Moreover, we propose a DEVS model notation based upon state chart XML to support a superior interoperability of different tool-chains.