A reconfigurable architecture specific for the butterfly computing

Morphosys is a reconfigurable single instruction multiple data (SIMD) architecture mainly composing of host core processor, reconfigurable cells array, frame buffer, context memory and direct memory access (DMA) module. As a common SIMD-based coarse-grained reconfigurable architecture, each context configuration and operation is based on the whole row or column function, which may be inefficient in some applications such as butterfly computing. In this paper, an improved reconfigurable architecture is proposed specific for butterfly computing application. The main work includes interconnection network design optimization, context memory architecture redefinition with quadrant binding, DMA channel addition and some other corresponding modification in reconfigurable cell. With these improvements, the new architecture can implement typical butterfly computing with cycle count about 5.53%~18.9% less than Morphosys.