A Low-Noise WLAN Mixer Using Switched Biasing Technique

A low-noise CMOS down-conversion mixer for WLAN applications is presented in this letter. The proposed mixer is based on the conventional Gilbert-type topology with switched biasing technique for a current source instead of static biasing, which lowers noise over a wide range of frequencies. Moreover, a dc level shifter is used for the symmetric switching operation in tail current transistors. A current bleeding technique is adopted to reduce the noise caused by the LO switching operation. The proposed mixer was fabricated using a 0.18 mum 1P6M CMOS process. Measurement results include a conversion gain of 7.5 dB, an IIP3 of -5 dBm, and noise figures of 10.9 dB at 1 MHz and 7.6 dB at 100 MHz. The mixer core consumes a current of 4.5 mA from a supply voltage of 1.8 V. The chip size, including pads for measurements, is 0.88 times 0.88 mm
²
.