Investigating Flash memory wear levelling and execution modes

The impact of wear levelling on a flash storage package and its access operations' execution modes is investigated. Simple, static logical to physical mapping functions are proposed and their implied wear levelling is assessed for different address distributions, covering both unifrom access and hot spots, as well as the flash chip utilisation within the whole package. For the access execution modes, different preemptive and non preemptive priority schemes are considered with a range of IO arrival rates using Poisson, Erlang and Pareto based arrival processes. The analysis of the impact of the execution modes on the performance of the flash memory is undertaken using a hardware simulator. The results obtained show clearly the good wear levelling obtained by the mapping functions, even in presence of hot spots and the effect of the chosen execution mode on the whole storage package for each IO workload type.