A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process

For the first time, we present good yielding 64Mb SRAM test-chip with the smallest cell using dual/triple gate oxide process flow in 28nm node. The low power technology platform continues scaling trend and extends SiON/poly technology beyond 32nm node with gate density of 2.3× higher than that of 45nm, and integrates high density (0.127um
²
) and low Vccmin (0.155um
²
) 6-T SRAM cells, low power transistors, analog/RF components and Cu-low-k interconnect [1]. Simultaneously available low standby (LSTP) and low operating power (LOP) transistors provide 25–40% speed improvement or 30–50% active power reduction over prior 45nm technology. Competitive mismatch (AVt of 2.86 mV.um) and 1/f noise characteristics, and enhanced MOM unit capacitance of 4.4 fF/um
²
(4 metal layers) with Q factor ≫100 at 2.4GHz are also achieved.