A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications: V
_t
< plusmn 0.45 V (at L
_g
= 60 nm) at EOT les 1.4 nm, with 10
⁵
times J
_g
reduction compared to SiO
₂
. This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaO
_x
/ AlO
_x
cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets.