Applications of advanced transmission electron microscopy techniques in gate stack scaling

Advanced gate dielectric stacks are comprised of multiple layers of different materials, including high-k gate dielectrics, high-mobility semiconductor channels, metal gate electrodes and interfacial layers with sub-nanometer thickness. The composition, point defect chemistry, interface atomic structure and interaction between the layers determine the properties of novel gate stacks. This paper reviews recent applications of advanced transmission electron microscopy techniques to determine the atomic structure and defects in advanced gate stacks.