Junction anneal sequence optimization for advanced high-k / metal gate CMOS technology

In this paper, we have done a comprehensive study of the junction anneal strategy (by spike and/or laser) for advanced technology nodes with Hk/MG and high-k capping film to control the eWF. It has been shown that a low long channel Vth is easily achievable with anneal sequence optimization. In particular with the help of laser which creates more dipoles for NMOS case with La-based capping. But also on PMOS due to a lower thermal budget which permits to avoid eWF modulation penalty for thin EOT. Good device scalability gain has been also achieved (10 and 15 nm for respectively NMOS and PMOS) with the sequence optimization without performance degradation.