Hardware Supported Time Synchronization in Multi-core Architectures

We present a design for a hardware supported global synchronization unit that would be implemented on-chip and directly accessible by all processors in a multi-core architecture. This global synchronization unit will provide all processors with access to global state information from all other processors in just a few clock ticks, and can be used to perform highly efficient and scalable time synchronization for parallel simulations. Further, our design takes into account the possibility of transient messages, and allows for non-uniform look ahead between processors in conservative synchronization methods. Simulating this hardware in a system simulator, we demonstrate its ability to decrease the runtime of a low-look ahead network simulation by a factor of two over a shared-memory barrier synchronization.