Flexible communication support for dynamically reconfigurable FPGAS

Dynamic reconfiguration of FPGAs allows the dynamic management of various tasks that describe an application. This new feature permits, for optimization purpose, to place tasks on line in an available region of the FPGA. Dynamic reconfiguration of tasks leads to some communication problems since tasks are not present in the matrix during all computation time. This dynamicity needs to be supported by the interconnection network. In this paper, we propose the implementation of a flexible interconnection network supporting such dynamicity. The proposed architecture is fully compliant with the present state-of-art dynamically reconfigurable circuits such as Xilinx Virtex family of FPGA.