High speed 3D acquisition chip design for robot applications

Obtaining automatic 3D profile of object is one of the most important issues in a robot vision system. We adopt one of the signal separation coding methods called Hierarchically Orthogonal Code(HOC) based on structured light in order to obtain robust depth imaging. To realize this algorithm, high-speed image processing is essential. Because this algorithm requires 17 raw-data pictures to get a picture containing depth information. Therefore, this paper introduces a high-speed hardware platform to perform 3D modeling. Firstly, we implement the platform using FPGA to verify the functionality of our design. Then, our design is fabricated using Samsung 0.18um CMOS technology. For the chip test, FPGA-based testing board was connected with components for image sensing. The results show that it requires 58 ms to generate one 3D image in realtime. This processing time is 14.5 times faster than the same implementation using software.