Interfacial Fracture Analysis of CMOS Cu/Low-$k$ BEOL Interconnect in Advanced Packaging Structures

The increasing use of Cu/low-k dielectrics as multilevel interconnect inclusion materials and aggressive scaling in advanced back-end of line (BEOL) results in a considerable challenge in the structural enhancement of mechanical reliability. Owing to the expected adoption of various ultra dielectrics, the development of a prediction methodology with reliable virtual prototypes is needed before realizing successful integrated circuits (IC) for the next technology node. These prototypes are required to assess the potentiality of interfacial cracks in dissimilar materials, while the impacts of chemical-mechanical polishing (CMP) and packaging are introduced. In order to meet the diversity of a Cu/low-k material system and to resolve the significant size difference between the interconnects and the whole IC device, this research presents finite element (FE) analysis based on the mechanic theory of interfacial fracture integrated with a global/local sub-modeling approach. The unique feature of the proposed novel concept is the adoption of equivalent stacked low-k interconnects within the analysis of a global FE model. Through estimation of the J-integral approach and verification of the four-point bending test (4-PBT), the methodology presented exhibits excellent numerical precision in predicting the cracking energy of low-k packaging. In addition, interfacial fracture parameters and stress fields acting near the crack tip are evaluated using an analytical solution combined with polynomial regressions. The derived results match well compared with the simulated data. Based on the presented demonstrations on the ability of simulated procedures, this investigation provides a desirable manner of understanding the related failure mechanisms of low-k interconnects.