FPGA implementation for an optimized CORDIC module for OFDM system

OFDM Wireless systems are currently in the focus of research and development. High hardware cost of such systems is an initiative to redesign the critical functional blocks in order to satisfy timing and power constrains as well as to minimize overall circuit complexity and cost. One such critical functional block is the CoOrdinate Rotation DIgital Computer (CORDIC) that can be used in various applications in OFDM systems. In this paper we apply optimization algorithms to the CORDIC processor in terms of power, area and speed for efficient FPGA implementation. Three CORDIC modules have been selected and modified to satisfy optimization requirements. The circuits have been described in Very high speed integrated circuit Hardware Description Language (VHDL), synthesized, and implemented on Xilinx Spartan-3A FPGAs kit board using ISEtrade design tool suite. The prototyped results have been tested using suitable testbench waveforms. Mapping and timing reports have been summarized. Using Matlab code relation between the delay for the published and prototyped modules has been plotted.